- 2025 阿里巴巴与XConn合作的工作PolarCXLMem发表 其中已有Memory Sharing的落地
- 2026-03-17 Marvell 发布通告，在OFC 2026展示Structera S系列CXL交换机。博客见：Structera S: Scaling the AI Memory Wall with CXL Switching，另见媒体通告Marvell Launches Next-generation CXL Switch, Enabling Memory Pooling to Break Through the AI “Memory Wall” 其中有提到上述工作，隐含支持sharing的意思
Structera S 30260 features support for 16 or 32 CPUs or GPUs over 260 lanes with up to 48TB of shared memory and 4TB/second cumulative bandwidth. Marvell is showcasing Structera S 30260 in a live demonstration this week at OFC 2026 and plans on sampling to customers in 3Q 2026.
The Marvell Structera S 30260 CXL switch is expected to begin sampling to customers in calendar Q3 2026. The Structera S 20256 CXL 2.0 switch is currently in production.
- 澜起科技的CXL 3.1实现：M88MX6852 | Montage Technology
- Panmnesic 支持PBR：Panmnesia Showcases PCIe 6.4 / CXL 3.2 Fabric Switch and Pilot System at CES 2026
- ASPLOS26: “Currently, there is no CPU or pool device that implements CXL 3.0 back invalidation flows, so cache-coherent sharing is unavailable [77]. Therefore, we distinguish between a non-coherent, realistic memory pool and a cachecoherent pool envisioned according to the specification.” 实际硬件已经支持PBR，但是是否实现了back-invalidation（BI）则是未知的
- 去年的HotOS文章则直接说明了BI尚且没有CPU和Device实现（需要两者配合）
“However, implementing BI involves both processorside and device-side changes, which greatly increases hardware complexity and costs. Neither CPUs nor CXL memory pool devices support BI today.”